1. Field of the Invention
The present invention relates to a chip package structure and a circuit board thereof, and more particularly to a chip package structure and a circuit board thereof capable of resisting stress generated when removing a redundant encapsulant.
2. Description of Related Art
In modern life with progressing science and technology, 3C electronic products are widely used in people's life. The electronic products are developed towards the trend of being light, thin, short and small along with the increasing progress of the trend. When the demand of people for electronic products increases, diverse peripheral components of the electronic products are emerged, in which circuit board is one of the indispensable components.
FIG. 1A is a schematic sectional view of a conventional chip package structure having a printed circuit board (PCB), and FIG. 1B is a schematic top view of a corner of the PCB in FIG. 1A. Referring to FIGS. 1A and 1B, the chip package structure 100 includes a PCB 160, a chip 140, and an encapsulant 150. The PCB 160 includes a substrate 110, a circuit layer 120, and a solder mask 130. The circuit layer 120 is disposed on the substrate 110, and includes a plurality of traces 122 and a plurality of via holes 124. The solder mask 130 covers the circuit layer 120 and the substrate 110, and has an encapsulant disposing area 132 for carrying the encapsulant 150. The traces 122 extend from the inside of the encapsulant disposing area 132 to the outside of the encapsulant disposing area 132. The chip 140 is located on the solder mask 130, and electrically connected to the trace 122. The encapsulant 150 covers the encapsulant disposing area 132 of the solder mask 130, and wraps the chip 140.
After forming the encapsulant 150, the redundant encapsulant 150 must be removed, and such removing action generates a stress on the trace 122 under the encapsulant 150. The trace 122 at the corner of the encapsulant disposing area 132 is located at a position where the stress is concentrated, and thus is easily to be pulled apart by the stress, which causes a decreased yield and poorer product reliability.
In order to reduce the probability of the trace being pulled apart by the stress, another conventional art provides a method in which no trace is disposed at the corner of the encapsulant disposing area. However, such a method reduces the area on the substrate available for disposing the circuit layer, so that the layout of the trace is more difficult to design.